IC Final Test


Brand Model Name
Chroma 3650 SOC Test System
Chroma 3360 VLSI Test System

Model 3650 SoC Test System

  • 50 /100 MHz
  • 512 digital I/O pins
  • 16/32 MW vector memory
  • 16/32 MW pattern instruction memory
  • Multi-site testing up to 32 sites
  • Per-pin test architecture
  • Up to 8 16-bit ADDA channels option
  • Up to 2Gbit X 8 CH scan depth option
  • ALPG option for memory test
  • Up to 32 high-voltage pins
  • 32 high-performance DPS channels
  • Overall timing accuracy < ±550ps
  • 8 ~ 32-CH / board for VI-45 analog option
  • 2 ~ 8-CH / board for PVI-100 analog option
  • MicrosoftWindows® XP OS
  • C++ and GUI programming interface
  • CRISP full suite of intuitive software tools
  • Test template for test program creation
  • Test program and pattern converters for other platforms
  • Accept DIB and probe card of other testers directly
  • Support STDF data output
  • Air-cooled, small footprint tester-in-a-test-head design

Chroma Model 3360 VLSI Test System

  • 50 MHz Test Rate(100Mhz HSCLK)
  • 608 I/O channels
  • 8~16 M Pattern Memory
  • Flexible Configuration (Interchangeable I/O, UVI, ADDA and LCD)
  • Parallel Testing for 32 devices
  • Real Parallel Trim/Match function
  • Accepts SC312, TS670 probe card
  • Test program/pattern converter (V7, TRI6020, V50, SC312, J750, ITS9K, TS670, ND1)
  • Analog PE card option (16 bit~24bit)
  • SCAN test option (512M)
  • ALPG test option for Memory
  • STDF tools support
  • User friendly Windows XP environment
  • CRAFT C/C++ programming language
  • Real time pattern editor with fail pin/fail address display
  • Versatile test analysis tools: Shmoo plot, Waveform display, Wafer Map, Pin Margin, Scope tool,Histogram tool and etc.

Chroma Model 3160 (Fingerprint) Quad Site Final Test Handler

  • Flexible DUT Configuration
  • Adjustable P&P Interval
  • Air damper buffer to reduce contact force impact
  • Intelligent socket IC leftover check
  • Auto Contact Force Learning
  • Color Tray Mode availability
  • Yield Monitor (per contact dead)
  • Yield Control (average yield rate of socket)
  • Compatible change kits with NS-5000 / 6000 / 6040


Testar provides Semiconductor Testing Service in Wafer Probing and Final Testing.

Our testing service covers a wide range of applications, such as logic devices, MCU, Interface controller IC, sensor controller, A/D and D/A converter,... etc. Which are mainly used in consumer electronics and communication devices.

Testar is capable to handle 5, 6, 8 and 12" wafers with inkless or off-line ink process inside our class-1K environment. Our Final Testing Service performs electrical testing as well as customized test items, program and parameters. The pick-and-place handler could cover diversified package type of devices.

Testar Semiconductor Tesing also provides below Engineering services to make your device fast "Time to Market",
  • Test program development 
  • Test program conversion 
  • Test Time reduction 
  • DFT consultant 
  • Multi-Site Testing development 



68,Hwa-Ya 1st Rd.,

Hwa-Ya Technology Park,

Taoyuan Hsien 333, Taiwan

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